Silicon-on-Insulator for Spintronic Applications: Spin Lifetime and Electric Spin Manipulation

With complementary metal-oxide semiconductor feature size rapidly approaching ultimate scaling limits, the electron spin attracts much attention as an alternative to the electron charge degree of freedom for low-power reprogrammable logic and nonvolatile memory applications. Silicon, the main element of microelectronics, appears to be the perfect material for spin-driven applications. Despite an impressive progress in understanding spin properties in metal-oxide-semiconductor field-effect transistors (MOSFETs), spin manipulation in a silicon channel by means of the electric field–dependent Rashba-like spin–orbit interaction requires channels much longer than 20 nm channel length of modern MOSFETs. Although a successful realization of the spin field-effect transistor seems to be unlikely without a new concept for an efficient way of spin manipulation in silicon by purely electrical means, it is demonstrated that shear strain dramatically reduces the spin relaxation, thus boosting the spin lifetime by an order of magnitude. Spin lifetime enhancement is achieved by lifting the degeneracy between the otherwise equivalent unprimed subbands by [110] uniaxial stress. The spin lifetime in stressed ultra-thin body silicon-on-insulator structures can reach values close to those in bulk silicon. Therefore, stressed silicon-on-insulator structures have a potential for spin interconnects.